Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - cpu verilog

Search list

[VHDL-FPGA-Verilog] mcpu_1.06b

Description: MCPU is a minimal cpu aimed to fit into a 32 Macrocell CPLD - one of the smallest available programmable logic devices. While this CPU is not powerful enough for real world applications it has proven itself as a valuable educational tool. The source code is just a single page and easily understood. Both VHDL and Verilog versions are supplied. The package comes with assembler, emulator and extensive documentation.-MCPU is a minimal cpu aimed to fit into a 32 Macrocell CPLD- one of the smallest available programmable logic devices. While this CPU is not powerful enough for real world applications it has proven itself as a valuable educational tool. The source code is just a single page and easily understood. Both VHDL and Verilog versions are supplied. The package comes with assembler, emulator and extensive documentation.
Platform: | Size: 248832 | Author: eldis | Hits:

[VHDL-FPGA-Verilog] KD_CPU_src

Description: verilog语言写的8位CPU源代码，基本的算术运算和逻辑运算，对于学习计算机原理和verilog语言都有良好的效果-Verilog Language Writing 8-bit CPU source code, the basic arithmetic operations and logic operations, the study of computer principles and Verilog language has good results
Platform: | Size: 57344 | Author: zz | Hits:

[VHDL-FPGA-Verilog] Microprocessor

Description: 精通verilog HDL语言编程的一个不错的cpu 代码-Verilog HDL language proficiency of a good cpu code
Platform: | Size: 774144 | Author: 孟霑 | Hits:

[VHDL-FPGA-Verilog] risc

Description: 用Verilog 编写的8位risc cpu，行为级描述，可综合-6 bits risc cpu by Verilog
Platform: | Size: 132096 | Author: 徐明 | Hits:

[Mathimatics-Numerical algorithms] dft

Description: verilog语言实在点变换DFT源代码，可以配合软核或者其他CPU进行综合FFT变换，也可以单独使用生成module！-verilog language is point FFT transform source code, can tie in with the soft-core CPU, or other integrated FFT transform, it can be used to generate module!
Platform: | Size: 1024 | Author: 刘庆 | Hits:

[VHDL-FPGA-Verilog] 8risc

Description: 8位RISC CPU,包括alu,count,machine-8 bit risc cpu
Platform: | Size: 3072 | Author: 刘成诚 | Hits:

[VHDL-FPGA-Verilog] verilog_design_a_simple_cpu

Description: 用verilog设计一个简单的cpu系统-Verilog design with a simple cpu system
Platform: | Size: 730112 | Author: jiangp | Hits:

[VHDL-FPGA-Verilog] lariviere2008uclinux

Description: xsoc vhdl verilog risc cpu soc implementation in very liitle cpld or fpga
Platform: | Size: 252928 | Author: urga turg | Hits:

[VHDL-FPGA-Verilog] timer

Description: 计时器的Verilog描述 CPU设计者可以借鉴 -Verilog decription of the timer in processors
Platform: | Size: 2048 | Author: Dee | Hits:

[VHDL-FPGA-Verilog] mips1

Description: Verilog MIPS design. I found it somewhere on Internet and it is working :-Verilog MIPS design. I found it somewhere on Internet and it is working :))))
Platform: | Size: 18432 | Author: Asparuh Grigorov | Hits:

[VHDL-FPGA-Verilog] 5_lined_cpu

Description: 简单5级流水线CPU的verilog逻辑设计-Simple line 5 of the CPU logic design verilog
Platform: | Size: 1024 | Author: 张健 | Hits:

[assembly language] 111m

Description: verilog code for cpu and bus.
Platform: | Size: 2048 | Author: Mohammad | Hits:

[Windows Develop] CPU_verilog

Description: 一个4级流水线CPU的verilog代码，供参考学习使用，有些语句不能综合，可以通过它学习CPU的工作原理。-A 4-stage pipeline CPU' s verilog code, learning to use for reference, some statements can not be integrated, you can learn from CPU through its works.
Platform: | Size: 63488 | Author: xq | Hits:

[source in ebook] CPU_code

Description: 基本的cpu verilog code 可用來瞭解基本cpu運作-Basic cpu verilog code can be used to understand the operation of the basic cpu
Platform: | Size: 347136 | Author: 吳小柔 | Hits:

[VHDL-FPGA-Verilog] cpu16

Description: Verilog下描述16位CPU，虽然有点简单，但具有一定的可读性，内附夏宇闻老师的8位CPU文档-Verilog description of 16-bit CPU, though a bit simple, but with a certain degree of readability, XIA Yu-Wen teachers containing 8-bit CPU Documentation
Platform: | Size: 231424 | Author: 张文龙 | Hits:

[source in ebook] Chapter1-5

Description: 第一章到第五章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter to Chapter V of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, function authentication, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 1580032 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] Chapter6-9

Description: 第六章到第九章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter VI to Chapter IX of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 6281216 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] 16_bits_CPU_verilog_code

Description: 利用Verilog设计的16位CPU的设计案例-the example of 16 bits CPU using verilog
Platform: | Size: 880640 | Author: 王惠娟 | Hits:

[Other Embeded program] RISCCPU

Description: 简单的CPU设计流程PPT，用于教学目的，可综合的verilog HDL设计。-A simple CPU design process PPT, for teaching purposes, can be integrated verilog HDL design.
Platform: | Size: 156672 | Author: 柳泽明 | Hits:

[SCM] W5300_Driver_V1[1].1.1

Description: 硬件TCPIP协议栈芯片W5300的使用例子代码,该芯片内部通过硬件实现了TCPIP协议栈,可减少CPU运行协议栈的开销.-Hardware TCPIP protocol stack chips W5300 examples of the use of code, the chip hardware implementation of the internal adoption of the TCPIP protocol stack can reduce the CPU overhead of running the protocol stack.
Platform: | Size: 35840 | Author: hengdao | Hits:
« 1 2 3 4 5 6 78 9 10 11 12 ... 20 »

CodeBus www.codebus.net